1. Field of the Invention
The invention relates to a process for fabricating MOSFET devices on a single semiconductor substrate, and, more particularly, to a process for providing MOSFET devices with improved control over threshold voltage and reduced parasitic conduction paths between neighboring transistors.
2. Description of the Prior Art
Processes for fabricating MOSFET (metal oxide semiconductor field effect transistor) devices, including both enhancement mode and depletion mode transistors, are wellknown. With improvements in reduction of spacing between devices as a consequence of improved photolithographic technology, parasitic conduction paths between neighboring transistors becomes a problem. Several approaches have been devised to eliminate parasitic conduction paths between transistors by heavily doping the intervening surface (the field region). U.S. Pat. Nos. 3,873,372 (Johnson), 4,074,301 (Paivinen et al) and 4,078,947 (Johnson et al) all teach different methods of achieving this. The difficulties encountered are (1) obtaining a low boron concentration in the MOSFET channel and (2) minimizing the separation between the high and low doped regions at the channel edge. Paivinen teaches eliminating parasitic conduction paths by implanting the wafer surface and then etching away the implanted material in the channel, source and drain regions. Johnson teaches using a nitride mask over the channel region. Johnson et al teach that the field adjusting implant can be done through an oxide. However, the difficulty with the Johnson et al technique is that the channel becomes heavily doped. A further problem with the Paivinen and Johnson et al patents is that the threshold voltage for enhancement mode (normally off) transistors is determined by an implant of boron. Consequently, low threshold voltages, on the order of a few tenths of a volt, are difficult to set accurately.